ASIC Engineer
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Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance die size optimization.
What you will do:
Who you are:
You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including:
You should also have hands on experience with the following Tool sets
Role: ASIC / RTL / Logic Design Engineer
Industry Type: IT Services & Consulting
Department: Engineering - Hardware & Networks
Employment Type: Full Time, Permanent
Role Category: Hardware
Education
UG: Any Graduate
PG: Any Postgraduate
Cisco has been active in India since 1995 and is a major contributor to the country's digital growth. India serves as Cisco’s second-largest research and development hub outside the U.S. The company supports digital initiatives in sectors like agriculture, education, and transportation. Through the Cisco Networking Academy, it also helps skill India’s tech workforce. In 2024, Cisco launched its first manufacturing unit in Chennai, aiming to boost local production and exports. This facility is expected to generate over $1.3 billion annually and create more than 1,200 jobs.
Job ID: 107746437
Skills:
C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification
Skills:
C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification
Skills:
Computer Architecture, integrated circuitry architectures, FPGA tools, programming and scripting hardware description language, digital logic, Design Verification, Vlsi Design
Skills:
Verilog, IEEE 1500, VHDL, ASIC Development, IEEE 1149.1, EDA tools for ASIC design verification and testing, Low-power design techniques
Skills:
Unix, Python, Lsf, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, GenAI, cdc, Design Verification, design layout constraints, CI CD process, DesignSync, UPF, SDC, Dft, RDC, EDA Tools, Graph Neural Networks, Implementation, make, reinforcement learning, debug tools, convolutional Networks, Power-aware flows, Clocks, SW development
