Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles

static timing analysis, Vc, Perl, Verilog, Python, Tcl, Power insertion, Synthesis, cdc, Design Auditor, structural RTL analysis, Linux development environments, meridian, systemverilog, SDC synthesis, spyglass, formal verification, RDC, Timing Constraints, LINT, equivalence checking, Questa CDC, low-power verification