Perl, Verilog, Python, Tcl, Circuit Design, Dc, ICC, Electrical Checks, systemverilog, Innovus, Physical Verification, Physical Design, Synthesis PnR, Genus, Deep Submicron Technology, device physics

Perforce, static timing analysis, Shell, Verilog, Version Control Systems, Scripting Languages, Python, Git, Perl, Tcl, cdc, Simulation, formal verification, EDA Tools, Rtl Design, Synthesis, SoC Architecture Design, LEC, AMBA protocols, systemverilog, Axi, APB, LINT, AHB, SoC Integration

System Verilog, Gate Level Simulations, Design Verification Fundamentals, formal verification, Interconnects, Coherency Concepts, NoCs, Automated Flows, Uvm

rtl development , Ecos, Spi, Constraints, I2c, Eeprom, Sta, memory integration, Digital Design, Uvm, Physical Design, Dft, formal verification, state machines, Verification, register maps, legacy code, Communication Protocols, Sram, EFuse, CDCs, Timing Constraints, RTL synthesis, digital concepts, I3C

C, Vcs, Perl, Verilog, Hardware Emulation Platforms, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

verification methodologies, power and signaling solutions, Physical Design, PD EDA flows