ASIC Digital Design, Staff Engineer - RTL Design

What You ll Need:

• BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows.
• Proficiency in running lint/cdc/rdc checks and synthesis flow.
• Experience in coding, verifying verilog and system verilog design.
• Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC
• Experience of leading technically for Front end activities.
• Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows.
• Scripting experience in Shell, Perl, Python, and TCL (preferred).