What You'll Be Doing:
- Work closely with 3DIO Phy Architects to define specifications and micro-architecture, supporting early evaluations and feasibility studies to meet customer and system requirements.
- Lead the execution of digital design solutions for 3DIO Phy projects, ensuring robust and high-performance designs.
- Own the implementation of RTL in Verilog and sign-off using Spyglass CDC/RDC/Lint tools.
- Verify the RTL to test desired functionality, coverage, and corner cases using state-of-the-art verification methods.
- Oversee the full execution of RTL2GDSII, including timing constraints, DFT insertion, test coverage, formal verification, physical implementation, timing closure, physical verification, EMIR, and reliability sign-off.
- Support silicon validation and characterization through test chip implementation.
- Manage team members and operations, including career development and planning.
The Impact You Will Have:
- Drive innovation in digital design solutions for 3DIO Phy projects, enhancing Synopsys product offerings.
- Ensure high-quality and robust designs that meet customer requirements and improve system performance.
- Streamline the digital design process from specification to silicon validation, reducing time-to-market.
- Lead a team of talented engineers, fostering a collaborative and productive work environment.
- Contribute to the continuous improvement of design methodologies and best practices.
- Support Synopsys position as a leader in the semiconductor industry through successful project deliveries.
What You ll Need:
- Excellent understanding of ASIC digital design flow with hands-on experience in HDL coding.
- Proficiency in writing synthesis constraints and basics of STA.
- Knowledge of Lint/CDC/RDC and RTL2GDSII flow.
- Working knowledge of scripting languages like Perl, Shell, Python, and Tcl.
- Experience in leading a small team of digital design engineers to execute projects.
- Knowledge of high-speed/DDR PHY Layer with lane redundancy implementation is highly desirable.
- Exposure to FIFO, test (ATE and characterization bench), silicon validation, and debugging.
- Familiarity with Synopsys toolset is highly desirable.
- Minimum 10 years of relevant digital design experience with at least 3 years as a people manager.
- B.E/B.Tech/M.Tech in ECE/EE.
Who You Are:
- Strong leadership skills with a proven track record of managing and developing teams.
- Excellent problem-solving abilities and attention to detail.
- Effective communication skills, both written and verbal.
- Ability to work collaboratively in a fast-paced, dynamic environment.
- Innovative and proactive mindset with a passion for continuous improvement
