ASIC Design Engineer Silicon

Responsibilities

• Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
• Perform RTL development (SystemVerilog), debug functional/performance simulations.
• Perform Register-Transfer Level (RTL) quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, Unified Power Format (UPF) checks.
• Participate in synthesis, timing/power estimation and Field Programmable Gate Array (FPGA)/silicon bring-up.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with digital design in ASIC.
• Experience with RTL design using Verilog/System Verilog and microarchitecture.
• Experience with ARM-based SoCs, interconnects and ASIC methodology.
• Experience with a scripting language like Python or Perl.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of industry experience with IP design.
• Experience with methodologies for low power estimation, timing closure, synthesis.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).