ASIC Design Engineer
- Posted 7 hours ago
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Job Description
Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
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Key Skills
About Company
AI/ML driven ASIC Design and Implementation Automation Lead EngineerNXP Semiconductors India Private Limited
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Skills:
Static timing analysis, Splunk, Unix, AI ML, Linux, Lsf, Python, Bitbucket, Jenkins, Git, DesignSync, EDA Tools, make, GenAI, Convolutional Networks, CI CD process, SW development and debug tools, Design Verification, reinforcement learning, Graph Neural Networks, Dft, Design revision control, Power-aware flows
Skills:
Lsf, Unix, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, Python, GenAI, VLSI CAD, CI CD process, DesignSync, make, reinforcement learning, Design revision control, Dft, Design Verification, EDA Tools, Power-aware flows, Convolutional Networks, Graph Neural Networks
Skills:
bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB
Skills:
Ecos, Tcl, Verilog, Python, DFT hooks, UPF, systemverilog, Ace, micro-architecture, low-power techniques, SVA, AHB, synthesis constraints, Timing Closure, APB, Axi, AMBA standard bus protocols