Application Specific Integrated Circuit Design Engineer
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LeadSoc Technologies is hiring!!
Senior RTL Engineers: 5-8 years
ASIC RTL Leads: 8 -12 years
Location: Bangalore
Exposure to subsystem or SOC level complexity involving connection and flows between components linked NOC, Peripherals, Microcontrollers.
Please share your profile to [Confidential Information] for further discussion.
Job ID: 131063617
Skills:
ARM debug architecture, IP design Subsystem Cluster and SoC level integration using Verilog System Verilog, Low Power, Synthesis, Timing Concepts, AMBA bus protocols AXI AHB ATB APB, Spyglass Lint CDC, SoC subsystem IP design, Processor Architecture, Synopsys DC, Verdi Xcellium, RTL quality checks Lint CDC
