Analog Layout engineers
- Posted a month ago
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Job Description
- Bachelor's or Master's Degree with 2-5 years of Analog Layout experience
- Good understanding of advanced semiconductor technology process and device physics.
- Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable :
Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc
- Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc)
- Experiences in advanced technology nodes under 32nm/28nm/16nm
- Experience with EMIR analysis, ESD, antenna and related layout solutions
- Good communication skills and willingness to work with global teams
- Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment
- Programming skills, automation and circuit Design background is a plus
More Info
Job Type:
Industry:
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Key Skills
Full-custom circuit layout verification
EMIR analysis
DRC
Mixed signal analog high speed layout
About Company
Skills:
Dac, ADC, Shielding Isolation, PEX, Matching Symmetry, LVS, Common Centroid, Pll, parasitics, advanced CMOS technology nodes, SERDES, Interdigitation, ERC, DRC, Op-Amp, Guard Rings, LDO, SKILL scripting, Analog Mixed-Signal blocks, layout-dependent effects, Bandgap, Cadence Virtuoso, PMIC
Skills:
analog layout techniques, Mentor tools, reliability requirements, LVS, Calibre, EMIR, Esd, ERC, Optimization, DRC, Parasitic Extraction, Antenna, Cadence Virtuoso, flat layout methodologies, layout tools