Analog Layout Engineer (4 - 8 Years)

Position: Junior/Senior Layout Engineer

Location: Bengaluru

Notice: Immediate

Experience: 4 - 8 Years

Company Description

SILCOSYS Solutions Pvt. Ltd. partners with leading global companies to develop their next-generation flagship product lines across mobile devices, networking equipment, consumer goods, storage solutions, microprocessors, graphics processors, and more. The organization focuses on pioneering advanced technologies that are both critical and uncommon in the semiconductor industry. SILCOSYS is recognized for its capability to design highly complex SoCs and deliver end-to-end solutions. The company further distinguishes itself through one of the industry's strongest analog/mixed-signal and software design teams, providing a dynamic environment for engineering professionals. Team members have opportunities to work on challenging projects that directly influence high-impact, market-leading products.

Role Description

This is a full-time, on-site Analog Layout Engineer role based in Bengaluru. The Analog Layout Engineer will be responsible for designing, implementing, and optimizing analog and mixed-signal IC layouts in collaboration with circuit design engineers. Day-to-day tasks include creating transistor-level layouts, floorplanning, and routing, while ensuring adherence to design rules, matching requirements, and performance specifications. The role involves performing layout verification (DRC/LVS, ERC, parasitic extraction), addressing design issues, and maintaining layout quality across multiple process technologies. The engineer will work closely with cross-functional teams, participate in design reviews, and contribute to continuous improvement of layout methodologies, tools, and best practices.

Qualifications

• Strong proficiency in analog and mixed-signal IC layout, including transistor-level layout, floorplanning, matching, and routing.
• Hands-on experience with industry-standard EDA tools (e.g., Cadence Virtuoso, Mentor/Siemens tools) and layout verification (DRC, LVS, ERC, parasitic extraction).
• Solid understanding of CMOS process technologies, device physics, and layout-dependent effects impacting performance, area, and reliability.
• Ability to interpret schematic circuits and specifications, and collaborate effectively with circuit design, verification, and physical design teams.
• Strong analytical, problem-solving, and documentation skills with attention to detail and adherence to design guidelines and schedules.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI Design, or a related field.
• Experience in complex SoC environments, high-speed or precision analog circuits, or mixed-signal IP (e.g., ADCs, PLLs, SERDES) is an advantage.
• Willingness to work on-site in Bengaluru and engage in fast-paced, technology-driven projects.

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