- Design and verify complex Analog Mixed-Signal (AMS) layouts ensuring IP quality and reliability
- Collaborate with cross-functional teams to optimize layout for performance, area, and manufacturability
- Address deep submicron effects using advanced tools and methodologies
- Perform floor-planning, routing, and top-level layout verification
- Ensure compliance with design standards including DRC, LVS, LPE, and account for ESD and latch-up
- Optimize power delivery networks with focus on EM/IR reliability
The Impact You Will Have:
- Improve performance and robustness of SerDes and other high-speed analog IP
- Contribute to cutting-edge AMS layout innovations for leading-edge process nodes
- Enable successful SoC integration through reliable and optimized physical designs
- Enhance product manufacturability and reduce design turnaround time
- Ensure consistent delivery of high-quality IPs that meet industry and customer standards
- Play a vital role in Synopsys mission to drive semiconductor technology forward
What You'll Need:
- 6+ years of experience in AMS layout and verification
- Strong knowledge of sub-28nm CMOS/FinFET process technologies
- Proficiency in layout tools and methodologies (Cadence, Calibre, etc.)
- Solid grasp of layout flow including top-level integration and verification
- Experience with ESD protection, latch-up prevention, and IR/EM optimization
- Strong communication, teamwork, and problem-solving skills
