Analog Layout Design Engineer
Location: Bengaluru (On-site / Hybrid)
Employment Type: Full-time
Experience: 2–8 years
Function: Semiconductor Engineering — Analog / Mixed-Signal Layout
About SiliconBoard
SiliconBoard connects semiconductor engineers with companies across the semiconductor ecosystem. This opportunity is offered through the SiliconBoard Talent Network. Shortlisted profiles are evaluated and shared with hiring companies for relevant open positions.
About the Role
We are looking for experienced Analog Layout Design Engineers with hands-on experience in custom analog and mixed-signal layout.
You will work on analog and mixed-signal IP across advanced process nodes, with responsibilities covering floorplanning, device placement, routing, physical verification, layout optimization, and sign-off.
Relevant block experience includes SERDES, PHY, PLL, ADC, DAC, LDO, Bandgap, charge pumps, comparators, current mirrors, differential amplifiers, and other high-speed or precision analog circuits.
Key Responsibilities
- Develop custom layouts for analog and mixed-signal circuits.
- Own block-level layout from initial floorplan through physical verification and sign-off.
- Perform device placement and routing with focus on matching, symmetry, shielding, isolation, and parasitic control.
- Work closely with circuit designers to understand performance requirements and layout constraints.
- Run and debug DRC and LVS checks.
- Identify and resolve layout-dependent performance issues.
- Optimize layout for area, performance, reliability, and manufacturability.
- Support integration of analog and mixed-signal IP into larger subsystems or full-chip designs.
- Work with design, verification, and physical integration teams through tapeout.
Required Qualifications
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
- 2–8 years of industry experience in Analog or Mixed-Signal Layout.
- Strong understanding of analog layout fundamentals including matching, symmetry, shielding, isolation, parasitic effects, and reliability.
- Hands-on experience with CMOS and/or FinFET technologies.
- Experience with DRC, LVS, and physical verification.
- Experience taking analog blocks from initial layout through sign-off.
- Ability to explain layout decisions, trade-offs, debugging methods, and implementation challenges from previous projects.
Preferred Qualifications
- Experience with process nodes such as 16nm, 12nm, 10nm, 7nm, 5nm, or 3nm.
- Experience with one or more of the following blocks:
- SERDES / PHY
- PLL
- ADC / DAC
- LDO
- Bandgap and reference circuits
- Charge pumps
- Current mirrors
- Comparators
- Differential amplifiers
- High-Speed IO
- Mixed-Signal IP
- Experience with full-chip AMS integration.
- Experience with layout-dependent effects, parasitic-aware design, and advanced-node layout constraints.
- Familiarity with industry-standard analog layout and physical verification tools such as Cadence Virtuoso, Calibre, Pegasus, or equivalent tools.
Hiring Process
- Submit your resume through the application link.
- Profiles are manually reviewed and shortlisted by the SiliconBoard team.
- Shortlisted candidates may receive a technical screening or interview.
- Qualified profiles are shared with the hiring company for the next stage of the process.
Additional Information
This role is with a SiliconBoard client company and not with SiliconBoard directly.
Compensation is determined by the hiring company based on experience, technical depth, current compensation, and role fit.
Submission of an application does not guarantee an interview or employment. Profiles are evaluated based on relevant project experience, technical depth, process-node exposure, block-level experience, and the requirements of the hiring company.
