Position - AMSV senior engineer
Roles and Responsibilities
- Perform Analog Mixed -Signal verification in different methodologies/flows (AXUM, AVUM , UVM-AMS).
- Review specifications, develop testcases independently as per the VPLAN.
- Strong debugging skills with respect to rtl, analog behavioural models and analog schematics
- Hands on technical experience in simulating testcases, debug SPICE and digital cosimulations for IPs, Subsystems and sub-blocks
- Understand analog and digital design intent, ensure correct test conditions, bug finding and reporting. Analyse results using waveform/debug tools and identify root cause for functional mismatch
- Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS, and optimize testbenches in tools like Xcelium, Cadence, or Synopsys flows.
- Maintain high level of professionalism in all tasks and interactions
- Meet deadlines with high quality deliverables
- Actively share skills, knowledge with team members and be proactive in technical discussions
- Perform any additional tasks as assigned by manager
Skills we are looking for:
- Strong understanding of of AMS verification methodologies including mixed signal cosimulation, assertion and checkers-based verification and analog behavioural modelling
- Advanced proficiency in EDA tools such as Cadence Virtuoso, Synopsys VCS and related verification platforms
- Good understanding of analog solver and simulator settings
- Excellent skills in Systemverilog, UVM and analog behivioral modelling languages (SV-RNM/Verilog-AMS/Verilog-A)
- Strong fundamentals of Analog and Digital concepts.
- Hands on experience with SPICE and digital simulation tools and debug environments
- Comfortable working in a collaborative team setup with clear communication
- Employ scripting languages (PERL, TCL, Python) for automation and efficiency in verification processes.
