design for test, IP Program Management, analog logic design, PNR, layout timing validation

Design-for-Test (DFT), C, C++, Static timing analysis, Perl, Verilog, Awk, Xml, Python, Tcl, LINT, cdc, Logic Synthesis, 28nm and smaller silicon process technologies, systemverilog, Cadence tool flows, DFT sign-off, VHDL, Scan testability, formal verification

layout verification , automation, DRC, Latch up, auto placement and route tools, LVS, Antenna Shield Matching, Ai, EM, Ir, analog mixed-signal, Documentation, Totem checks, Layout Design, custom digital block, full chip level, standard cells, skill coding

Packaging, Layout Design, digital layout, SI PI, Circuit Design, mixed-signal circuits

Scripting Languages, Sta, Synthesis, Flow development, PNR, Digital Implementation flow, debugging skills, ML based Solutions