code coverage , Verilog, System Verilog, AHB, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, ip development, functional coverage, front-end design tools

Perl, Verilog, Python, Tcl, formal verification with Cadence LEC, Netlist CLP, Spyglass Lint CDC checks, UPF, clock domain crossing designs, Rtl Design, Synthesis, Logical Equivalence checks, low power design methodology

Perl, Python, Tcl, CDC Lint, low power design, digital circuit design principles, RDC, Timing Analysis Concepts, RTL design synthesis, UPF

DDR, Pcie, Verilog, synthesis constraints, clock reset expertise, coherency memory subsystems, AMBA protocols, systemverilog, ECO flows, Dft, performance power analysis, ASIC RTL, cross-team collaboration, low-power design, security blocks, micro-architecture, SVA