Ovm, Vcs, Debugging, Scripting Languages, Unix Environment, Verilog, System Verilog, Test plan development, IP level verification, Auto checking verification, Mixed signal verification, NCSim, Questasim, Coverage assertion driven verification, Uvm, Testbench development, Real number modeling, Functional Code Coverage, VMM, NCVerilog, Simulation

ASIC SoC physical design, place-and-route, fabrication process limitations, Cadence Innovus, Physical Verification, EM analysis, floorplanning