Fpga, Verilog, I2c, System Verilog, Synthesis, cdc, constraint development, Simulation Tools, Cadence, VHDL, RDC, digital timing analysis, LINT, RTL Coding, ASI, audio signal chain, Digital Design, TDM

Design for Manufacturing (DFM), Design for Testability (DFT), RDC (Reset Domain Crossing), CDC (Clock Domain Crossing), hardware description languages (HDLs) such as Verilog and SystemVerilog or VHDL, static timing analysis, Uvm, Synthesis, Simulation, multi-power-domain design techniques, formal verification tools such as Siemens Questa Formal and Synopsys Spyglass, digital design flow, FPGA design methodologies

FPGA Design, Verilog, Perl, Static Timing, Python, Tcl, ASIC design flow, systemverilog, CMOS digital circuits, Rtl Design, Dft, Front-end tools, Firmware development for test systems, High-speed data transmission, Clock design, Verification, Synthesis, Datapath timing analysis, Mixed signal concepts, Digital design principles

Verilog, UNIX, ASIC SoC design methodologies, design quality checks, simulation debugging, Ms Office Tools, digital design RTL coding, systemverilog, Windows environments

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Questa, spyglass, LINT, Xcelium, cdc, Sec, Jasper-FPV, Questa CDC, RDC