Verilog, systemverilog

Makefile, C, Systemc, Windows, Linux, Verilog, Shell, Ruby, System Verilog, Perl, graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, HLS tools, UVM testbenches, TLM, UVM based verification frameworks, simulation profile efficiency improvement

gate level simulations, Logic schematic analysis, Verilog simulations, SystemVerilog PLI coding, AI-assisted tools, Timing Analysis, UVM Test Bench