design for test, Silicon Development, IP Program Management, analog logic design, PNR, Mixed Signal Design, IP development process, layout timing validation

Design-for-Test (DFT), C, C++, Static timing analysis, Perl, Verilog, Awk, Xml, Python, Tcl, LINT, cdc, Logic Synthesis, 28nm and smaller silicon process technologies, systemverilog, Cadence tool flows, DFT sign-off, VHDL, Scan testability, formal verification

Scripting Languages, Sta, Synthesis, Flow development, PNR, Digital Implementation flow, debugging skills, ML based Solutions