rtl development , Usb, Pcie, Ethernet, Physical Design, UFS, Vlsi, Timing, Verification, Digital Design, micro-architecture

UVM (Universal Verification Methodology), Tcl, Mercurial, Svn, DDR, Git, Perl, Pcie, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, C/C++, System Verilog Assertions, Design Verification infrastructure

Static timing analysis, Splunk, Unix, AI ML, Linux, Lsf, Python, Bitbucket, Jenkins, Git, DesignSync, EDA Tools, make, GenAI, Convolutional Networks, CI CD process, SW development and debug tools, Design Verification, reinforcement learning, Graph Neural Networks, Dft, Design revision control, Power-aware flows

Spi, Uart, Verilog, I2c, AHB, LINT, AMBA bus protocols, SoC integration, cdc, RTL Coding, MAS development, Quality check flows, ip design, Microarchitecture, APB, Axi, Medium complexity protocol, Sub-system design