Out of Order Super Scalar Multi-Threaded Core Architecture, Processor Core silicon bring up, RTL design with Verilog or VHDL, High frequency instruction pipeline designs

Perl, Verilog, Python, logic design optimization, Timing Analysis, validation workflows, systemverilog, IP RTL design, System Verification, Microarchitecture

Pcie, Verilog, Ethernet, Synthesis, cdc, UALink, Simulation, timing considerations, UCIe, systemverilog, LINT, CXL