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Lead FPGA Timing & Characterization Silicon Design Engineer

We are seeking a highly motivated and experienced Senior Member of Technical Staff (SMTS) to lead the development, validation, silicon correlation, and release of FPGA timing models. The successful candidate will drive timing characterization methodologies, improve timing model quality and accuracy, collaborate across architecture, silicon design, STA, software, and validation teams, and ensure timely delivery of production-quality timing models that enable industry-leading FPGA implementation and timing analysis tools.

Roles and Responsibilities

Establish comprehensive validation frameworks for FPGA timing library quality assessment.
Drive root-cause analysis for timing discrepancies and model inaccuracies.
Develop and maintain regression suites, DRC checks, and release signoff criteria.
Drive characterization of FPGA resources
Develop automation flows to improve FPGA timing quality
Own planning and execution of Timing Library releases aligned with software release schedules.
Perform QoR analysis on Vivado software and compare timing results across releases, speed grades, and device generations.
Coordinate release readiness reviews and manage risk mitigation plans.
Provide technical status updates to engineering leadership and product stakeholders.

Required Qualifications

MTech or MS in Electronics Engineering.
10+ years of experience in FPGA design development & implementation, timing analysis, Silicon characterization
Strong understanding of:

FPGA architecture and timing closure
Static Timing Analysis (STA), PVT variation and timing margins, OCV/POCV methodologies

Experience with silicon characterization and model generation flows.
Proficiency in scripting and automation using Python, Perl, Tcl, or similar languages.
Strong debugging and root-cause analysis skills.
Familiarity with large-scale flow automation and data analytics.
Experience with Vivado or Quartus FPGA tools
Knowledge of silicon correlation and statistical timing techniques.
Experience leading cross-functional technical initiatives.

Expectations:

Serve as the technical authority for FPGA timing library methodologies and releases.
Drive improvements in prediction accuracy, release quality, and characterization productivity.
Influence roadmaps, timing methodologies, and next-generation FPGA timing modeling strategies.
Mentor engineers and establish engineering best practices across the organization.
Lead technically challenging projects with significant product and customer impact.

Success Metrics

On-time delivery of timing library releases.
Silicon correlation accuracy improvement.
Reduction in customer timing escapes.
Improved QoR consistency across releases.
Increased automation and productivity of characterization flows.
Successful execution of strategic timing-modeling initiatives.

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Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available

This posting is for an existing vacancy.