Tcp, Pcie, Ethernet, System Verilog, Gate Level Simulations, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Vcs, Perl, Python, Tcl, Questa, Verdi, XSIM, AMBA protocols, Uvm, systemverilog, Axi, APB, DVE, AHB

Tcp, System Verilog, Ethernet, Pcie, formal verification, Forwarding logic Parsers P4, Verifying sophisticated blocks clusters and top level for ASIC, Building test benches from scratch, RDMA, Zebu, System Verilog constraints structures and classes, HAPS, ASIC verification using UVM, Palladium, Veloce