C, C++, Makefile, Windows, Shell, Linux, Verilog, System Verilog, Python, IP level ASIC verification, SystemVerilog language, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, UVM concepts, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, testbenches processes and flows

Makefile, Verilog, System Verilog, C, Python, UVM concepts, Debugging firmware and RTL code using simulation tools, UVM testbenches, HLS tools, Developing UVM based verification frameworks, Simulation profile efficiency improvement, IP level ASIC verification