Design-for-Test (DFT), Verilog, System Verilog, Rtl Design, Physical design considerations, Timing Closure, SoC development, Microarchitecture development, Low-power design methodologies, Architecture Design

static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, digital IC ASIC design, low-power design techniques, RTL quality tools such as Spyglass Lint CDC RDC