EDA tools such as virtuoso extraction and DRC LVS, ESD layouts EM IR flows, abstract view generation, high-speed analog layout, parasitic optimization, Artificial Intelligence tools such as Co-pilot Claude, floorplan power planning, device matching, SKILL or one of the scripting languages, technology nodes like 16nm and below

power integrity , Emc, HDI routing, DFA, fine-pitch BGA components, Emi, return-current paths, Cadence Allegro PCB Designer, microvias, Constraint Manager, via-in-pad, Dfm, high-speed digital mixed-signal analog RF and power-supply layout practices, PCB layout design, Signal Integrity, Dft, PDN implementation, crosstalk, blind buried vias, back-drilling, thermal considerations, IPC-based PCB design practices

layout interaction, Synopsys Custom Compiler, high-speed interfaces, post-layout verification, BERTs, design sign-off, Analog Circuit Design, Spectre, transistor-level design, Hspice, Parasitic Extraction, silicon bring-up, mixed-signal IC design, Cadence Virtuoso, behavioral modeling, high-speed oscilloscopes