device physics matching techniques, Bandgaps, Custom Analog Layout, Mentor Graphics verification tools Calibre, Oscillators, ADCs, analog and mixed-signal layout techniques, Cadence Layout tools Virtuoso, DACs, Temperature Sensor, Bias Circuits, OPAMP circuits, Physical Verification LVS DRC ERC ANT with Calibre, LDOs, ESD Latchup mitigation techniques, circuit parasitic extraction reduction, VXL compliance

Mentor Graphic Calibre DRC, Full chip level integration support, TSMC 3nm, Cadence VLE, Design and development of critical analog mixed-signal custom digital block