Perl, Python, Tcl, formal verification, JasperGold, VC-Formal, systemverilog, SVA

automation, Python, Tcl, place-and-route, Cadence Innovus, Timing Analysis, Physical Verification

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, Cadence Virtuoso, 3DIC implementation methodologies, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Perl, Verilog, Vcs, Gdb, Python, Rtl Design, System-On-Chip design implementation, Debussy, Design Automation, dc shell

C, Uart, Bash, Spi, DDR, Pcie, Perl, Verilog, I2c, System Verilog, Python, Tcl, i2s, DFX Verification, Uvm, Axi, APB, AHB

Perl, Python, Tcl, CDC Lint, low power design, digital circuit design principles, RDC, Timing Analysis Concepts, RTL design synthesis, UPF

synopsys primetime , Python Scripting, Formality, STA PrimeTime, Physical-aware synthesis flows, Fusion Compiler, Design Compiler, SDC constraint authoring and management, Physical-Aware Synthesis