Automation Scripting, AI-assisted workflows, FinFET, LVS, Dfm, Physical Verification, CMOS, bicmos, EMIR, SiGe, ERC, EDA Tools, DRC, RF layouts, Cadence Virtuoso

shielding , Pvs, Crosstalk, LVS, MUX Control Blocks, Latch-up, Sense Amplifiers, Assura, Memory Compiler, Esd, Critical Signal Routing, Antenna, DRAM, Memory Periphery Circuits, Cadence VLE, Calibre DRC, EM, IR-drop, Sram, Custom Memory Layouts, LVS DRC debugging, Bitcell Arrays, Memory Layout Design, Rom, Flash Memory Layout Design, Wordline Decoders, Rf, ERC

Device Matching, ESD LU protection techniques, Power Bus design, Full chip layout experience, LVS DRC ERC and antenna debug skills, Automation SKILL coding, Analog and mixed-signal layout techniques

Python, Pvs, Tcl, Circuit Analysis, Power Routing, Collaboration, Physical Verification, Calibre, ESD Latch-Up, Verification, Project Cycles, Floorplan to Tape-out, Reliability Effects, Layout Techniques, Scripting in SKILL, Cadence Virtuoso, Assura, FinFET nodes, LDE Reliability, Analog RF Layout, Methodology

Electromigration EM, IR drop and reliability constraints, DRC LVS tools Calibre Assura PVS, Cadence Virtuoso, ESD protection concepts, Latch-up prevention, Voltage isolation and guard ring planning, Layout-dependent effects LDE

Pvs, Analog layout design, die-to-bump connectivity, package substrate interactions, PEX, R3D, analog layout matching techniques, EM, Ir, IC Layout design, LVS, CAD Tools, Floor Planning, Calibre, Xl, Esd, DRC, PowerFET, virtuoso, Packaging

Quality Assurance, SPICE Circuit Simulators, Circuit Design, Layout Automation Techniques, MOSFET Electrical Behavior, Standard Cell Layout Design, Transistor-Level Device Physics, Standard Cell EDA Views, PPA Performance, Layout Methodologies, Characterization Modeling, CMOS Design Principles

layout verification , automation, Mentor Graphic Calibre DRC, AI tools, Layout Design, skill coding, Cadence VLE