cdc, Bit-exact model correlation, Register interface, numerical acceptance criteria, AMBA AHB APB, AMBA bus integration, UVM-based verification, Clock domain crossing, on-chip bus integration, timing closure awareness, programmable digital filters, mixed-signal SoCs, fixed-point arithmetic, Timing Closure, Verilog RTL design, high-throughput data paths, reset architecture

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso

Unix, Lsf, Constraints, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, CI/CD, Low Power, Slurm

Fc, Python, Tcl, Digital VLSI implementation, Sta, primetime, Innovus, EDA Tools, Tempus, PNR implementation, ML algorithms and techniques

Perl, Verilog, Python, scripting and automation tools, ISO26262, Formal verification methodologies, ADCs, Cadence, Automotive qualification, Uvm, systemverilog, Analog Circuit Design, DACs, Comparators, Op-Amps