Static Dynamic EM IR-drop Analysis, Power Grids, Signal Integrity, Low-Power Design Strategies, 16nm, Physical Design, 5nm, Timing Closure, 7nm, EDA Tools, RTL-to-GDSII, CTS Architecture

hardware engineering , Static Timing Analysis (STA), Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation

Perl, Tcl, Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation, tapeout experience