bandwidth management , Machine Learning, Artificial Intelligence, SystemVerilog Assertions, Specman E, Debug, formal tools, IP subsystem SoCs, congestion control, AI ML accelerators, systemverilog, memory system architecture, vector processing units, ASIC standard interfaces, packet processing, Verification, Universal Verification Methodology

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso

Pcie, Perl, Vcs, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog

Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB

Tcp, Pcie, Ethernet, System Verilog, Gate Level Simulations, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

System Verilog, testbench stimulus agent monitor checker development, C based system modelling, Emulation, Uvm, Power aware simulation, tensilica, gate level simulation, formal verification, sub-system verification, C based reference model, failure debugging with Verdi log file, assertion development

Shell, Perl, Verilog, Python, Tcl, Functional and code coverage, Simulation and debugging concepts, Automation scripts, Assertions SVA, UVM methodology, systemverilog

Vcs, UVM SoC environment, End-to-end datapath verification methodologies, Xcelium, Questa, Waveform analysis tools, DFT simulation and validation, systemverilog, Clock reset verification