Design-for-Test (DFT), Vcs, System Verilog, DFT CAD development, Test Static Timing Analysis, Logic Equivalency checking, Post-silicon validation, P1687, Scan and BIST architectures, Gate level simulation debugging, Verilog design, ATE patterns, JTAG protocols, ATPG, Test Architecture Methodology

boundary scan , Vcs, Python, Perl, Tcl, Scan Insertion, sdf debugging, DFT CAD development, Jtag protocols, DFT logic IP integration, p1687, p1500, EDA Tools, BIST architectures, Test static timing analysis, Tessent tool sets, Test Architecture Methodology, Infrastructure, memory BIST, TetraMax, Verilog design, Functional Verification, ATPG, Gate level simulation, Timing Closure, timing based simulations, TestMax

amazon emr , Scala, Apache Spark, Python, Sql

Rust, Docker, Kernel Programming, Python, Linux systems expertise, IPsec and SSL VPN protocols, Virtualization experience, Go, C/C++, CI/CD proficiency