Shell, C, PERL, Makefile, PYTHON, C++, Uvm, UPF based low power design verification, Functional Verification, formal verification

Verification IP (VIP), Vcs, Python Scripting, Verilog, Assembly Programming, Test plan development, UVM methodology, systemverilog, SoC-level verification, Verilog C Co-Simulation, Directed and random drivers, Testbench architecture

Debugging, systemverilog, industry-standard simulators, Verification Tools, RTL design concepts, simulation debug methodologies, UVM-based verification methodologies, assertions, coverage-driven verification, SVA, constrained-random verification