simvision , Unix, Vcs, Shell Scripting, Linux, Perl, Python, Verdi, Power-aware simulation, Gate-Level Simulation, Xcelium, Timing validation, Uvm, Netlist-based verification, systemverilog, SDF annotation, DVE, RTL-to-Gate correlation, Questa, SVA SystemVerilog Assertions

Tcp, Pcie, Ethernet, System Verilog, Gate Level Simulations, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

System Verilog, testbench stimulus agent monitor checker development, C based system modelling, Emulation, Uvm, Power aware simulation, tensilica, gate level simulation, formal verification, sub-system verification, C based reference model, failure debugging with Verdi log file, assertion development

Shell, Perl, Verilog, Python, Tcl, Functional and code coverage, Simulation and debugging concepts, Automation scripts, Assertions SVA, UVM methodology, systemverilog

Perl, Verilog, Shell scripting, System Verilog, Python, test bench development, coverage assertion writing, Uvm

clocking , Ovm, DDR, Pcie, Verilog, Ethernet, Platform bring up in Emulators or Silicon, SOC boot flow, Constrained-random verification environments, Uvm, systemverilog, Power management flows, C SV tests, HSIO, Low Power Verification, Coverage report generation, System Verilog Assertions, RTL GLS level simulations

Shell, Perl, Python, Tcl, Test Cases, Cadence Xcelium, Mentor QuestaSim, Synopsys VCS, Constrained Random Verification, Functional Verification, PCI Express PCIe protocol, ASIC SoC Design Verification, Functional Coverage Models, Verification Plans, Waveform analysis, Assertion-Based Verification SVA, Simulation Tools, SystemVerilog UVM, Testbenches, Assertions

bandwidth management , Microprocessor Cores, SystemVerilog Assertions, Specman E, systemverilog, hierarchical memory subsystems, Debug, formal tools, IP subsystem SoCs, packet processing, constrained-random verification environments, Verification, congestion control

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4