Process design rules, Layout methodologies, Analog layout design, Electron migration, Voltage drop, High speed SerDes layouts, Micro-floor planning, IR ESD, TSMC N3 technology, Power grid, ESD bumps, Signal planning, Floorplans, Design verification tools

Pvs, Analog layout design, die-to-bump connectivity, package substrate interactions, PEX, R3D, analog layout matching techniques, EM, Ir, IC Layout design, LVS, CAD Tools, Floor Planning, Calibre, Xl, Esd, DRC, PowerFET, virtuoso, Packaging