Perl scripting, Verilog, C, Python, Uvm, AHB, systemverilog, Axi

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso

System Verilog, dv methodologies and tools, DDR LPDDR families, Digital design concepts, Debug, Uvm

bus protocols - APB, C, Bash, Spi, Pcie, Verilog, I2c, System Verilog, Python, Usb, Uart, Perl, Test Plan Creation, Tcl, gate-level simulations, verification methodology, Uvm, DP, Sd, AHB, Test Development, Gate Level Power-Aware simulations, Axi, i2s, test-bench development, test coverage assessment

OASIS, Verilog, Python, Shell, Perl, Tcl, PERC, LVS, Physical Design, Dfm, CDL, SVRF-based automation, XOR methodologies, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII

C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog, SVA