Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB

Vcs, UVM SoC environment, End-to-end datapath verification methodologies, Xcelium, Questa, Waveform analysis tools, DFT simulation and validation, systemverilog, Clock reset verification

clocking , Ovm, DDR, Pcie, Verilog, Ethernet, Platform bring up in Emulators or Silicon, SOC boot flow, Constrained-random verification environments, Uvm, systemverilog, Power management flows, C SV tests, HSIO, Low Power Verification, Coverage report generation, System Verilog Assertions, RTL GLS level simulations

Noc, Usb, DDR, Pcie, Perl, Ethernet, Python, Tcl, SVA, Functional Coverage, Uvm, systemverilog, DDR5, LPDDR, DDR4

Test Case Creation, Python, Perl, Shell, Formal Verification techniques, Advanced Debugging skills, Uvm, Rtl Design, testbench development, coverage-driven verification, Computer Architecture concepts, Functional Verification

Tcl, Shell scripting, Vcs, Usb, Ethernet, Python, Pcie, Perl, DDR, Questa, Uvm, systemverilog, Xcelium

Vcs, Integration, System Verilog, Synopsys VIPs, processor based SoC level verification, ASIC Design, AXI-AMBA protocol, Verification, Uvm, Validation, waveform analyzer

Test Planning, C, Pcie, C++, Debugging, Soc Architecture, Test Development, Functional Verification, Uvm, UCIe, systemverilog

C, Tcl, Python, Perl, AHB, GLS, SystemRDL, Uvm, UPF, systemverilog, RAL, IP-XACT, Tk, APB, Axi