Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA

Usb, Nvme, Pcie, Python Programming, C Programming, Protocol analyzers, Logic Analyzers, USD, Oscilloscopes, Sd, Flash Memory, Function Generators

Perl, Shell Scripting, Python, Tcl, Formal Verification Techniques, Mixed-Signal Verification, systemverilog

Fpga, Vcs, Pcie, Ethernet, Xcelium, Emulation, Uvm, systemverilog, Dft, Questa, DDR5, DDR4

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

UVM (Universal Verification Methodology), Tcl, Mercurial, Svn, DDR, Git, Perl, Pcie, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, C/C++, System Verilog Assertions, Design Verification infrastructure