Gate Level Simulations, Tessent EDT, Genus FC Scan Insertion, Tessent MBIST, Timing, OCC SSN ATPG, NoTiming

Verilog, Usb, Tcl, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, LINT, ASIC design flow, Timing Analysis, peripheral IPs, Synthesis, Low-power design, Axi, power estimations, BUS Protocols, MBIST, Bus Matrix design, MIPS, AMBA, Rtl Design, timing constraint SDC, DFT concepts, RDC, Formal CDC

MBIST, HDLs, ATPG flow implementation, Tempus, DFT architecture definition, JTAG boundary scan insertion, Pattern Simulation, Scan, Genus, Cadence digital implementation tools