redhawk , Perl, Fc, Tcl, IR drop, high performance and low power implementation methods, Tweaker, Physical design STA in CPU Domain, Pt, Tempus, Physical PT ECOs, Physical Verification, Innovus, deep submicron process technology nodes, preparing complex ECOs for timing convergence, Genus, Voltas, floorplan to PRO and timing signoff

manufacturing processes , tolerance analysis , Solidworks, Bom, Catia, Sheet Metal, DFA, supplier coordination, Fea, Cost Analysis, plastics materials, Cae, Vehicle Integration, Dfm, surface modelling, cross-functional collaboration, Product Development, Dfmea

Testing, Prototyping, circuit design debugging, hardware-software integration, hardware validation, circuit development, Embedded Systems, FPGA programming, Pcb Design, IoT hardware

Rtl Design, micro-architecture, LINT, low power checks, Synthesis, Sta

Verilog, ASIC RTL, Dft, Synthesis constraints, Micro-architecture skills, Clock reset expertise, Architecture skills, AMBA protocols, Low-power design, systemverilog, ECO flows

Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Tcl, Perl, Python, Memory Architecture, LVS closure, Analog custom layout techniques, FinFET technology nodes, CMOS layout fundamentals, Symmetry, Physical verification flows, Custom memory layout design, Cadence Virtuoso, Device matching, Parasitic Extraction, DRC closure