power optimization , Integration, Perl Scripting, Tcl, CTS, advanced STA concepts, Block level PnR convergence, Cadence Innovus, LVS, PTSI Tempus, timing convergence, Physical Verification, Timing Closure, ASIC Design, DRC, Verification, PDN, Physical Design Implementation, Floor-planning, Place And Route, Validation, Synopsys ICC2, formal verification

flows and methodologies, Asic Physical Design, collaboration and teamwork, EDA vendor relationships

coverage analysis, Integration of multiple IPs, UVM-based test plan development, SoC-level verification, Scalable verification infrastructures, AI-driven verification methodologies, Emulation, Low-power verification methodologies, Power-aware verification, Sequence generation, Hybrid verification flows, Coherency protocols, formal verification, FPGA prototyping

Pcie, Nvme, SAS, Silicon Validation, physical implementation, Dft, RTL design using Verilog, Timing Closure, CXL, Uvm, systemverilog