Perl, Verilog, Python, Rtl Design, logic design optimization, Timing Analysis, validation workflows, systemverilog

micro architecture , X86, Computer Architecture, Arm, Processor Asic design flow, ECO bring up, Design Verification, Fetch Decode Load-Store, high performance microprocessor architecture, L1 L2 caches, Coherency, CPU microarchitecture, Memory Design, Processor Instruction set architecture, PD synthesis, Rtl Design, Prefetch, Memory Ordering Rules, PPA optimization, Power

Pcie, Verilog, Ethernet, Synthesis, cdc, UALink, Simulation, timing considerations, UCIe, systemverilog, LINT, CXL