OASIS, Verilog, Python, Shell, Perl, Tcl, PERC, LVS, Physical Design, Dfm, CDL, SVRF-based automation, XOR methodologies, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII

static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols

Networking, Sql, Java, AWS, Nosql, Python, Kubernetes, Gcp, Apache Kafka, Cloud Security, Cloud Computing, GCP Pub Sub, Ai

Shell, Perl, Python, Tcl, power analysis, RTL simulation, Design Verification, clock gating, Uvm, GLS, activity analysis, Simulation emulation, power-aware verification, vector development, power states, Retention

Static Timing Analysis (STA), PERL, Python, Tcl, Synthesis, Cadence

C, C++, Dac, Scripting, Python, LabVIEW, ADC, mixed-signal ICs, sensing solutions, lab instrumentation, AFE data-acquisition, analog signal-chains, embedded MCU, RISC-V, Pcb Design, reference designs, PGAs, evaluation boards, sensor excitation, low-noise amps, precision power supplies, ARM subsystems