static timing analysis, Rtl Design, Synthesis, RISC CPU IP, Emulation, silicon bring-up, Microarchitecture, Verification, equivalence checking, Physical Design, CDC linting

synopsys primetime , Perl, Python, Tcl, Unified Power Format UPF, Tweaker, Constraints Validation Synopsys TCM GCA Ausdia TimeVision SpyGlass Constraints, Cadence CCD, Sign-off STA Synopsys PrimeTime PT PT-PX, PrimeClosure, Cadence Tempus, Synopsys Formality, Timing Closure ECO Cadence Tempus

Unix Shell, DDR, Pcie, Perl, Ethernet, Python, Tcl, SOC inter-connect buses, Palladium, coding in scripting languages, Processor Architecture, SOC components, IO protocols, Zebu, HBM, Veloce, CXL, memory technologies, emulation platforms

static timing analysis, LINT, Logic Synthesis, cdc, formal verification, Dft, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

Scripting Languages, C Programming, Mass storage interface protocol PCIe NVMe, Firmware design and debug, Test equipment such as oscilloscopes and logic bus analyzers, ARM development tools and IDE such as Eclipse, Programming tools and environments

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, LVS, Voltus, MMMC, Timing Closure, DRC, EM IR analysis, full-chip implementation