Schematic Design, Control-Loop Stability, power management, Analog Layout Effects, ESD Latch-Up, Mixed-Signal IC Development, Protection Circuits, Switching Converters, Extraction, Post-Layout Verification, Analog Design, References, Sensors, Data Converters, Charge Pumps, Signal-Conditioning Blocks, Simulation, IC-Level Robustness, LDOs, Analog Feedback Loops

shielding , custom layout design, signal flow optimization, isolation, device matching, LVS, Power Planning, layout architecture, IR optimization, clock routing, parasitic minimization, power routing, biasing, EDA Tools, ERC, DRC, Cadence Virtuoso, EM IR latch-up prevention, parasitic management, ESD protection

multi-domain clock synchronization, spyglass, high-speed serial interfaces, Verplex LEC, ASIC debugging, high-performance memory subsystems, Synopsys Design Compiler, Verilog RTL coding

static timing analysis, Verilog, VHDL, Xcelium, RTL Coding, design-for-test

DVCS e.g. Git, Sql, C, Xpath, Gcc, HTML, Xslt, Dom, Linux, Xml, Python, Javascript, LLVM, Uvm, SGE or other DRMS, systemverilog, Assembly languages, SVA

Tcl, Python, Perl, Spice simulations, ASIC back-end flows, Timing Constraints, AOCV, Monte Carlo analysis, noise, cross-talk, STA fundamentals, Hspice, POCV concepts, CTS, Innovus, ICC2, primetime, Tempus, Signal Integrity, Parasitic Extraction, scripting proficiency, STA tools, FineSim

rtl development , data movement, Verilog, Computer Architecture, CDC reset architecture, microarchitecture development, coherent fabrics, networking interconnect concepts, hardware design methodology, high-speed interconnects, systemverilog