Unix, Lsf, Constraints, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, CI/CD, Low Power, Slurm

C++, Openmp, Valgrind, Hpc, RDMA, SVE, ARM Neon, MPI, RoCE, simd, AVX-512, DPDK, ARM diagnostics, Purify

Numpy, Git, Pytorch, Pandas, Python, OpenAI’s GPT models, Hugging Face, prompt engineering

System Verilog, Gate Level Simulations, Building test benches from scratch, ASIC verification using UVM, formal verification

C, Uart, Bash, Spi, DDR, Pcie, Perl, Verilog, I2c, System Verilog, Python, Tcl, i2s, DFX Verification, Uvm, Axi, APB, AHB

data engineering , react.js , Data Modelling, Azure Data Bricks, Microservices, Data Quality, Typescript, Distributed Systems, Rest Apis, Python, LLMs, RAG systems, vector databases, agent frameworks, AI integration, large-scale data processing, ETL pipelines

static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols

Networking, Sql, Java, AWS, Nosql, Python, Kubernetes, Gcp, Apache Kafka, Cloud Security, Cloud Computing, GCP Pub Sub, Ai