Java, Cassandra, Spring Boot, Kafka, J2EE, Spring Cloud, Google Cloud, Spring, Microservices, Jms, Docker, MySQL, Openshift, MongoDB, Oracle, Azure, Kubernetes, AWS, CI/CD

Oracle Integration Cloud (OIC), Visual Builder Cloud Service (VBCS), Soap Services, Pl Sql, Sql, Bi Reports, Git, Xml, Api Management, OCI GenAI Agents, Agile Scrum methodologies, DevOps practices, Oracle Fusion AI Agent Studio, AI-powered integrations, XSLT transformations, OCI services, OCI Generative AI, OAuth security protocols, Oracle Cloud adapters, CI/CD pipelines, encryption standards

OASIS, Verilog, Python, Shell, Perl, Tcl, PERC, LVS, Physical Design, Dfm, CDL, SVRF-based automation, XOR methodologies, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII

analog layout techniques, circuit architectures, power management ICs, ESD latch-up, analog circuit design fundamentals, simulation methodologies, transistor-level analog IC design, analog IP development, chip-level reliability considerations

Numpy, Git, Pytorch, Pandas, Python, OpenAI’s GPT models, Hugging Face, prompt engineering

Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design

static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols