Unix, Lsf, Constraints, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, CI/CD, Low Power, Slurm

Numpy, Git, Pytorch, Pandas, Python, OpenAI’s GPT models, Hugging Face, prompt engineering

Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design

data engineering , react.js , Data Modelling, Azure Data Bricks, Microservices, Data Quality, Typescript, Distributed Systems, Rest Apis, Python, LLMs, RAG systems, vector databases, agent frameworks, AI integration, large-scale data processing, ETL pipelines

static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols