Dft, SSN OCC TAP verification, scan patterns generation, Post silicon debug, multi die DFT, ICL simulations, ATPG, scan-stitching, Tessent ATPG, timing and no-timing simulations, Pattern retargeting

Sed, Jtag, Awk, Tcl, Dft, Tessent, ATPG, Scan, MBIST, LBIST, Spyglass-DFT

scan patterns generation, SSN OCC TAP verification, multi die DFT, Post silicon debug, ICL simulations, ATPG, scan-stitching, Tessent ATPG, timing and no-timing simulations, Pattern retargeting

Jtag, DFT Engineer, DFT Manager, iJTAG, BSCAN, ATPG, technical ownership, DFT tools

DFx techniques, ASST implementation, Gate level simulation using Synopsys VCS and Verdi, MBIST planning implementation and verification, DFT Architectures, Uvm, RTL coding for DFx logic, ATPG and test coverage analysis, JTAG Scan Compression, systemverilog, low-power design flows, Fault Campaigns, Fault Models, ATPG and DFx insertion CAD tools, post-silicon testing

Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), Design for Testability (DFT), Jtag, Perl, Tcl, Cadence Tools, Dft, Scan Compression, BSCAN, Compression Testing