power integrity , DDR, Pcie, Cadence, GDDR, High-speed interface IPs, Timing Closure, Physical Design, SERDES, EDA Tools, LPDDR, Synopsys, Signal Integrity

Tcl, Python, Perl, Innovus, Sign-off, Power Grid, SI crosstalk analysis, Tempus STA, ECO generation, pegasus, Calibre, floorplanning, CTS, Sta, MMMC, GDSII, Cadence Toolchain, Timing Closure

hardware engineering , Static Timing Analysis (STA), Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation

Scripting, Static Timing Analysis, Routing, Design Compiler, CTS, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Formal Equivalence, Extraction, StarRC, Placement, RTL to GDS2 flow, Floor-plan Physical Implementation, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

Clock Planning, Physical Verification, floorplanning, Placement and Routing, Timing Closure, Physical Design Implementation

Perl, Tcl, Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation, tapeout experience

System on a Chip (SoC), Design for Testing (DFT), Very-Large-Scale Integration (VLSI) design, Static Timing Analysis (STA), coding constraints, scripting with TCL, low power designs